The present invention relates generally to a system for generating an oscillator signal and, more specifically, to a phase-locked loop (PLL) system for generating an oscillator signal.
A phase-locked loop (PLL) is a system that generates an oscillator signal having a constant phase relationship with an input reference signal. PLL systems are widely used in various applications such as radio, telecommunications, computers, and other electronic applications. A PLL system includes a voltage-controlled oscillator (VCO) for generating the oscillator signal based on a control voltage, and a phase detector for comparing the phase of the oscillator signal with that of the input reference signal and for generating an error signal based on the detected phase difference. The PLL system also includes a loop filter for filtering the error signal and generating the control voltage. Thereafter, the control voltage is provided to the VCO.
Generally, PLL systems are expected to operate over a wide range of frequencies and over a wide range of process, voltage and temperature (PVT) variations. To operate over a wide range of frequencies, a common practice is to increase the VCO gain. However, the increase in VCO gain makes the VCO more susceptible to phase noise. Further, lack of immunity to phase noise results in high output jitter.
In one approach used for reducing VCO gain, the loop bandwidth of the PLL system is reduced. The loop bandwidth refers to the range of frequencies over which the VCO can operate. However, reduced loop bandwidth limits the operating range of the PLL system. Further, to reduce jitter, the loop bandwidth should be set as high as possible. Hence, reducing the loop bandwidth results in having a narrow operating frequency range and poor jitter performance.
In certain PLL systems, input reference signal frequency may be tracked using a charge pump circuit. The charge pump circuit generates a charge pump current based on the error signal generated by the phase detector. However, this approach does not reduce the gain of the VCO. Further, to control variations in VCO gain, additional components must be included, which increases the size of the PLL system.
To minimize the gain of the VCO over a wide operating range, external calibration circuits are used for calibrating the VCO. During calibration, the calibration circuit coarse tunes the VCO close to a locking frequency, while keeping the PLL system in an open loop. Thereafter, the VCO is fine tuned to the locking frequency by closing the loop. The gain of the VCO is minimized as the VCO is primarily tuned by the calibration circuit. However, the calibration of the VCO does not help in reducing variations in VCO gain with respect to PVT variations. The gain variations result in variable phase margin and bandwidth, thereby leading to unstable operation of the PLL system. Further, VCO gain variations reduce the flexibility of circuit design.
It would be advantageous to have a PLL system that has low VCO gain over a wide operating range and low VCO gain variations with respect to PVT variations.